DPsim
DP_Ph1_RxLine.cpp
1 /* Copyright 2017-2021 Institute for Automation of Complex Power Systems,
2  * EONERC, RWTH Aachen University
3  *
4  * This Source Code Form is subject to the terms of the Mozilla Public
5  * License, v. 2.0. If a copy of the MPL was not distributed with this
6  * file, You can obtain one at https://mozilla.org/MPL/2.0/.
7  *********************************************************************************/
8 
9 #include <dpsim-models/DP/DP_Ph1_RxLine.h>
10 
11 using namespace CPS;
12 
13 DP::Ph1::RxLine::RxLine(String uid, String name, Logger::Level logLevel)
14  : Base::Ph1::PiLine(mAttributes),
15  CompositePowerComp<Complex>(uid, name, true, true, logLevel) {
16  setVirtualNodeNumber(1);
17  setTerminalNumber(2);
18 
19  SPDLOG_LOGGER_INFO(mSLog, "Create {} {}", this->type(), name);
20  **mIntfVoltage = MatrixComp::Zero(1, 1);
21  **mIntfCurrent = MatrixComp::Zero(1, 1);
22 }
23 
26  auto copy = RxLine::make(name, mLogLevel);
27  copy->setParameters(**mSeriesRes, **mSeriesInd);
28  return copy;
29 }
30 
32 
33  (**mIntfVoltage)(0, 0) = initialSingleVoltage(1) - initialSingleVoltage(0);
34  Complex impedance = {**mSeriesRes, **mSeriesInd * 2. * PI * frequency};
35  (**mIntfCurrent)(0, 0) = 0;
36  mVirtualNodes[0]->setInitialVoltage(initialSingleVoltage(0) +
37  (**mIntfCurrent)(0, 0) * **mSeriesRes);
38 
39  // Default model with virtual node in between
40  mSubResistor =
41  std::make_shared<DP::Ph1::Resistor>(**mName + "_res", mLogLevel);
42  mSubResistor->setParameters(**mSeriesRes);
43  mSubResistor->connect({mTerminals[0]->node(), mVirtualNodes[0]});
44  mSubResistor->initialize(mFrequencies);
45  mSubResistor->initializeFromNodesAndTerminals(frequency);
46  addMNASubComponent(mSubResistor, MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
47  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, false);
48 
49  mSubInductor =
50  std::make_shared<DP::Ph1::Inductor>(**mName + "_ind", mLogLevel);
51  mSubInductor->setParameters(**mSeriesInd);
52  mSubInductor->connect({mVirtualNodes[0], mTerminals[1]->node()});
53  mSubInductor->initialize(mFrequencies);
54  mSubInductor->initializeFromNodesAndTerminals(frequency);
55  addMNASubComponent(mSubInductor, MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
56  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, true);
57 
58  mInitialResistor =
59  std::make_shared<DP::Ph1::Resistor>(**mName + "_snubber_res", mLogLevel);
60  mInitialResistor->setParameters(1e6);
61  mInitialResistor->connect({SimNode::GND, mTerminals[1]->node()});
62  mInitialResistor->initialize(mFrequencies);
63  mInitialResistor->initializeFromNodesAndTerminals(frequency);
64  addMNASubComponent(mInitialResistor,
65  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
66  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, false);
67 
68  SPDLOG_LOGGER_INFO(mSLog,
69  "\n--- Initialization from powerflow ---"
70  "\nVoltage across: {:s}"
71  "\nCurrent: {:s}"
72  "\nTerminal 0 voltage: {:s}"
73  "\nTerminal 1 voltage: {:s}"
74  "\n--- Initialization from powerflow finished ---",
75  Logger::phasorToString((**mIntfVoltage)(0, 0)),
76  Logger::phasorToString((**mIntfCurrent)(0, 0)),
77  Logger::phasorToString(initialSingleVoltage(0)),
78  Logger::phasorToString(initialSingleVoltage(1)));
79 }
80 
81 void DP::Ph1::RxLine::mnaParentPreStep(Real time, Int timeStepCount) {
82  mnaCompApplyRightSideVectorStamp(**mRightVector);
83 }
84 
85 void DP::Ph1::RxLine::mnaParentAddPreStepDependencies(
86  AttributeBase::List &prevStepDependencies,
87  AttributeBase::List &attributeDependencies,
88  AttributeBase::List &modifiedAttributes) {
89  modifiedAttributes.push_back(mRightVector);
90 }
91 
92 void DP::Ph1::RxLine::mnaParentAddPostStepDependencies(
93  AttributeBase::List &prevStepDependencies,
94  AttributeBase::List &attributeDependencies,
95  AttributeBase::List &modifiedAttributes,
96  Attribute<Matrix>::Ptr &leftVector) {
97  attributeDependencies.push_back(leftVector);
98  modifiedAttributes.push_back(mIntfCurrent);
99  modifiedAttributes.push_back(mIntfVoltage);
100 }
101 
102 void DP::Ph1::RxLine::mnaParentPostStep(Real time, Int timeStepCount,
103  Attribute<Matrix>::Ptr &leftVector) {
104  mnaCompUpdateVoltage(**leftVector);
105  mnaCompUpdateCurrent(**leftVector);
106 }
107 
108 void DP::Ph1::RxLine::mnaCompUpdateVoltage(const Matrix &leftVector) {
109  (**mIntfVoltage)(0, 0) = 0;
110  if (terminalNotGrounded(1))
111  (**mIntfVoltage)(0, 0) =
112  Math::complexFromVectorElement(leftVector, matrixNodeIndex(1));
113  if (terminalNotGrounded(0))
114  (**mIntfVoltage)(0, 0) =
115  (**mIntfVoltage)(0, 0) -
116  Math::complexFromVectorElement(leftVector, matrixNodeIndex(0));
117 }
118 
119 void DP::Ph1::RxLine::mnaCompUpdateCurrent(const Matrix &leftVector) {
120  (**mIntfCurrent)(0, 0) = mSubInductor->intfCurrent()(0, 0);
121 }
Base class for composite power components.
PI-line dynamic phasor model.
Definition: DP_Ph1_PiLine.h:28
void initializeFromNodesAndTerminals(Real frequency) override
Initializes component from power flow data.
SimPowerComp< Complex >::Ptr clone(String name) override
DEPRECATED: Delete method.
void mnaParentPreStep(Real time, Int timeStepCount) override
MNA pre and post step operations.
RxLine(String uid, String name, Logger::Level logLevel=Logger::Level::off)
Defines UID, name, logging level.
String type()
Get component type (cross-platform)
Base class for all components that are transmitting power.
Definition: SimPowerComp.h:17
const Attribute< MatrixVar< Complex > >::Ptr mIntfCurrent
Current through component.
Definition: SimPowerComp.h:47
const Attribute< MatrixVar< Complex > >::Ptr mIntfVoltage
Voltage between terminals.
Definition: SimPowerComp.h:45
Logger::Log mSLog
Component logger.