DPsim
DP_Ph1_PiLine.cpp
1 /* Copyright 2017-2021 Institute for Automation of Complex Power Systems,
2  * EONERC, RWTH Aachen University
3  *
4  * This Source Code Form is subject to the terms of the Mozilla Public
5  * License, v. 2.0. If a copy of the MPL was not distributed with this
6  * file, You can obtain one at https://mozilla.org/MPL/2.0/.
7  *********************************************************************************/
8 
9 #include <dpsim-models/DP/DP_Ph1_PiLine.h>
10 
11 using namespace CPS;
12 
13 DP::Ph1::PiLine::PiLine(String uid, String name, Logger::Level logLevel)
14  : Base::Ph1::PiLine(mAttributes),
15  CompositePowerComp<Complex>(uid, name, true, true, logLevel) {
16  setVirtualNodeNumber(1);
17  setTerminalNumber(2);
18 
19  SPDLOG_LOGGER_INFO(mSLog, "Create {} {}", this->type(), name);
20  **mIntfVoltage = MatrixComp::Zero(1, 1);
21  **mIntfCurrent = MatrixComp::Zero(1, 1);
22 }
23 
26  auto copy = PiLine::make(name, mLogLevel);
27  copy->setParameters(**mSeriesRes, **mSeriesInd, **mParallelCap,
28  **mParallelCond);
29  return copy;
30 }
31 
33 
34  // Static calculation
35  Real omega = 2. * PI * frequency;
36  Complex impedance = {**mSeriesRes, omega * **mSeriesInd};
37  (**mIntfVoltage)(0, 0) = initialSingleVoltage(1) - initialSingleVoltage(0);
38  (**mIntfCurrent)(0, 0) = (**mIntfVoltage)(0, 0) / impedance;
39 
40  // Initialization of virtual node
41  mVirtualNodes[0]->setInitialVoltage(initialSingleVoltage(0) +
42  (**mIntfCurrent)(0, 0) * **mSeriesRes);
43 
44  // Create series sub components
45  mSubSeriesResistor =
46  std::make_shared<DP::Ph1::Resistor>(**mName + "_res", mLogLevel);
47  mSubSeriesResistor->setParameters(**mSeriesRes);
48  mSubSeriesResistor->connect({mTerminals[0]->node(), mVirtualNodes[0]});
49  mSubSeriesResistor->initialize(mFrequencies);
50  mSubSeriesResistor->initializeFromNodesAndTerminals(frequency);
51  addMNASubComponent(mSubSeriesResistor,
52  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
53  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, false);
54 
55  mSubSeriesInductor =
56  std::make_shared<DP::Ph1::Inductor>(**mName + "_ind", mLogLevel);
57  mSubSeriesInductor->setParameters(**mSeriesInd);
58  mSubSeriesInductor->connect({mVirtualNodes[0], mTerminals[1]->node()});
59  mSubSeriesInductor->initialize(mFrequencies);
60  mSubSeriesInductor->initializeFromNodesAndTerminals(frequency);
61  addMNASubComponent(mSubSeriesInductor,
62  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
63  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, true);
64 
65  // By default there is always a small conductance to ground to
66  // avoid problems with floating nodes.
67  Real defaultParallelCond = 1e-6;
68  **mParallelCond =
69  (**mParallelCond > 0) ? **mParallelCond : defaultParallelCond;
70 
71  // Create parallel sub components
72  mSubParallelResistor0 =
73  std::make_shared<DP::Ph1::Resistor>(**mName + "_con0", mLogLevel);
74  mSubParallelResistor0->setParameters(2. / **mParallelCond);
75  mSubParallelResistor0->connect(
76  SimNode::List{SimNode::GND, mTerminals[0]->node()});
77  mSubParallelResistor0->initialize(mFrequencies);
78  mSubParallelResistor0->initializeFromNodesAndTerminals(frequency);
79  addMNASubComponent(mSubParallelResistor0,
80  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
81  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, false);
82 
83  mSubParallelResistor1 =
84  std::make_shared<DP::Ph1::Resistor>(**mName + "_con1", mLogLevel);
85  mSubParallelResistor1->setParameters(2. / **mParallelCond);
86  mSubParallelResistor1->connect(
87  SimNode::List{SimNode::GND, mTerminals[1]->node()});
88  mSubParallelResistor1->initialize(mFrequencies);
89  mSubParallelResistor1->initializeFromNodesAndTerminals(frequency);
90  addMNASubComponent(mSubParallelResistor1,
91  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
92  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, false);
93 
94  if (**mParallelCap >= 0) {
95  mSubParallelCapacitor0 =
96  std::make_shared<DP::Ph1::Capacitor>(**mName + "_cap0", mLogLevel);
97  mSubParallelCapacitor0->setParameters(**mParallelCap / 2.);
98  mSubParallelCapacitor0->connect(
99  SimNode::List{SimNode::GND, mTerminals[0]->node()});
100  mSubParallelCapacitor0->initialize(mFrequencies);
101  mSubParallelCapacitor0->initializeFromNodesAndTerminals(frequency);
102  addMNASubComponent(mSubParallelCapacitor0,
103  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
104  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, true);
105 
106  mSubParallelCapacitor1 =
107  std::make_shared<DP::Ph1::Capacitor>(**mName + "_cap1", mLogLevel);
108  mSubParallelCapacitor1->setParameters(**mParallelCap / 2.);
109  mSubParallelCapacitor1->connect(
110  SimNode::List{SimNode::GND, mTerminals[1]->node()});
111  mSubParallelCapacitor1->initialize(mFrequencies);
112  mSubParallelCapacitor1->initializeFromNodesAndTerminals(frequency);
113  addMNASubComponent(mSubParallelCapacitor1,
114  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT,
115  MNA_SUBCOMP_TASK_ORDER::TASK_BEFORE_PARENT, true);
116  }
117 
118  SPDLOG_LOGGER_INFO(
119  mSLog,
120  "\n--- Initialization from powerflow ---"
121  "\nVoltage across: {:s}"
122  "\nCurrent: {:s}"
123  "\nTerminal 0 voltage: {:s}"
124  "\nTerminal 1 voltage: {:s}"
125  "\nVirtual Node 1 voltage: {:s}"
126  "\n--- Initialization from powerflow finished ---",
127  Logger::phasorToString((**mIntfVoltage)(0, 0)),
128  Logger::phasorToString((**mIntfCurrent)(0, 0)),
129  Logger::phasorToString(initialSingleVoltage(0)),
130  Logger::phasorToString(initialSingleVoltage(1)),
131  Logger::phasorToString(mVirtualNodes[0]->initialSingleVoltage()));
132 }
133 
135  AttributeBase::List &prevStepDependencies,
136  AttributeBase::List &attributeDependencies,
137  AttributeBase::List &modifiedAttributes) {
138  // add pre-step dependencies of component itself
139  prevStepDependencies.push_back(mIntfCurrent);
140  prevStepDependencies.push_back(mIntfVoltage);
141  modifiedAttributes.push_back(mRightVector);
142 }
143 
144 void DP::Ph1::PiLine::mnaParentPreStep(Real time, Int timeStepCount) {
145  // pre-step of component itself
146  this->mnaApplyRightSideVectorStamp(**mRightVector);
147 }
148 
149 void DP::Ph1::PiLine::mnaParentAddPostStepDependencies(
150  AttributeBase::List &prevStepDependencies,
151  AttributeBase::List &attributeDependencies,
152  AttributeBase::List &modifiedAttributes,
153  Attribute<Matrix>::Ptr &leftVector) {
154  // add post-step dependencies of component itself
155  attributeDependencies.push_back(leftVector);
156  modifiedAttributes.push_back(mIntfVoltage);
157  modifiedAttributes.push_back(mIntfCurrent);
158 }
159 
160 void DP::Ph1::PiLine::mnaParentPostStep(Real time, Int timeStepCount,
161  Attribute<Matrix>::Ptr &leftVector) {
162  // post-step of component itself
163  this->mnaUpdateVoltage(**leftVector);
164  this->mnaUpdateCurrent(**leftVector);
165 }
166 
167 void DP::Ph1::PiLine::mnaCompUpdateVoltage(const Matrix &leftVector) {
168  (**mIntfVoltage)(0, 0) = 0;
169  if (terminalNotGrounded(1))
170  (**mIntfVoltage)(0, 0) =
171  Math::complexFromVectorElement(leftVector, matrixNodeIndex(1));
172  if (terminalNotGrounded(0))
173  (**mIntfVoltage)(0, 0) =
174  (**mIntfVoltage)(0, 0) -
175  Math::complexFromVectorElement(leftVector, matrixNodeIndex(0));
176 }
177 
178 void DP::Ph1::PiLine::mnaCompUpdateCurrent(const Matrix &leftVector) {
179  (**mIntfCurrent)(0, 0) = mSubSeriesInductor->intfCurrent()(0, 0);
180 }
181 
182 MNAInterface::List DP::Ph1::PiLine::mnaTearGroundComponents() {
183  MNAInterface::List gndComponents;
184 
185  gndComponents.push_back(mSubParallelResistor0);
186  gndComponents.push_back(mSubParallelResistor1);
187 
188  if (**mParallelCap >= 0) {
189  gndComponents.push_back(mSubParallelCapacitor0);
190  gndComponents.push_back(mSubParallelCapacitor1);
191  }
192 
193  return gndComponents;
194 }
195 
196 void DP::Ph1::PiLine::mnaTearInitialize(Real omega, Real timeStep) {
197  mSubSeriesResistor->mnaTearSetIdx(mTearIdx);
198  mSubSeriesResistor->mnaTearInitialize(omega, timeStep);
199  mSubSeriesInductor->mnaTearSetIdx(mTearIdx);
200  mSubSeriesInductor->mnaTearInitialize(omega, timeStep);
201 }
202 
203 void DP::Ph1::PiLine::mnaTearApplyMatrixStamp(SparseMatrixRow &tearMatrix) {
204  mSubSeriesResistor->mnaTearApplyMatrixStamp(tearMatrix);
205  mSubSeriesInductor->mnaTearApplyMatrixStamp(tearMatrix);
206 }
207 
208 void DP::Ph1::PiLine::mnaTearApplyVoltageStamp(Matrix &voltageVector) {
209  mSubSeriesInductor->mnaTearApplyVoltageStamp(voltageVector);
210 }
211 
212 void DP::Ph1::PiLine::mnaTearPostStep(Complex voltage, Complex current) {
213  mSubSeriesInductor->mnaTearPostStep(voltage - current * **mSeriesRes,
214  current);
215 }
Base class for composite power components.
PI-line dynamic phasor model.
Definition: DP_Ph1_PiLine.h:28
void mnaParentPreStep(Real time, Int timeStepCount) override
MNA pre and post step operations.
SimPowerComp< Complex >::Ptr clone(String copySuffix) override
DEPRECATED: Remove method.
void mnaCompUpdateCurrent(const Matrix &leftVector) override
Updates internal current variable of the component.
void initializeFromNodesAndTerminals(Real frequency) override
Initializes component from power flow data.
PiLine(String uid, String name, Logger::Level logLevel=Logger::Level::off)
Defines UID, name and logging level.
void mnaParentAddPreStepDependencies(AttributeBase::List &prevStepDependencies, AttributeBase::List &attributeDependencies, AttributeBase::List &modifiedAttributes) override
add MNA pre and post step dependencies
void mnaCompUpdateVoltage(const Matrix &leftVector) override
Updates internal voltage variable of the component.
String type()
Get component type (cross-platform)
Base class for all components that are transmitting power.
Definition: SimPowerComp.h:17
const Attribute< MatrixVar< Complex > >::Ptr mIntfCurrent
Current through component.
Definition: SimPowerComp.h:47
const Attribute< MatrixVar< Complex > >::Ptr mIntfVoltage
Voltage between terminals.
Definition: SimPowerComp.h:45
Logger::Log mSLog
Component logger.